FIG. 15 shows a conventional digital feedback clamping circuit whose output is processed by an A/D converter. Referring to the figure, an input signal from an input terminal 1 is clamped by a clamping circuit 2 to a predetermined clamping potential during a period of a clamping pulse from a terminal 3. The clamped signal is then A/D-converted by an A/D converter 4 and then fed to an output terminal 5.
A part of the output signal from the A/D converter 4 is supplied to a difference detector 6, in which it is compared with a reference potential (or clamping potential) during a period of a pulse indicative of a reference potential period (or clamping potential period) supplied from a terminal 7. Then, a difference therebetween is amplified by an inverting amplifier 8, D/A-converted by a D/A converter 9 and then supplied through a low-pass filter 10 to the clamping circuit 2 as the clamping potential, thereby effecting a feedback operation such that both inputs to the difference detector 6 become always constant.
In the case of the feedback clamping circuit constructed as shown in FIG. 15, if the gain of the amplifier 8 and the time constant of the low-pass filter 10 in the feedback loop are made constant when the noise amount of the input terminal from the input terminal 1 is large, then the clamping potential applied to the clamping circuit 2 will fluctuate in accordance with the level of the noise. To solve this problem, the gain of the amplifier 8 must be lowered or the time constant of the low-pass filter 10 must be increased, which degrades the clamping capability.
In view of the above aspect, the present invention is to provide a clamping circuit which can effect the stable clamping operation even when a source is a source having a large noise amount.
A feedback clamping circuit according to a first aspect of the present invention comprises an identifying means 20 for identifying a digital control code signal previously involved in an input signal and a gain control means 8 for controlling a gain or dead area width of a feedback loop in response to an output of the identifying means 20, wherein a clamping control is effected by utilizing a digital information.
A feedback clamping circuit according to a second aspect of the present invention comprises a noise detecting means 30 for detecting an amount of noise involved in an input signal and a gain control means 8 for controlling a gain or dead area width of a feedback loop in response to an output of the noise detecting means 30, wherein a clamping control is effected by utilizing a digital information.
According to the first aspect of the present invention, the identifying means 20 identifies the digital control code signal and the gain control means 8 controls the gain or dead area width of the feedback loop in response to the detected output. That is, when the digital control code signal is a code representative of a signal having a poor S/N ratio, a gain decrease area or dead area width is widened in response to the kind of input signal, while when it is a code representative of a signal having an excellent S/N ratio, the gain decrease area or dead area width is narrowed.
Furthermore, according to the second aspect of the present invention, the noise detecting means 30 detects an amount of noise contained in the input signal and the gain control means 8 controls the gain or dead area width of the feedback loop in response to a detected output thereof. That is, when the amount of noise contained in the input signal is large, then the gain decrease area or dead area width is widened, while when it is small, then the gain decrease area or dead area width is narrowed. According to the invention in any of its aspects, even when an input signal having relatively large amount of noise is input to the feedback clamping circuit, the clamping potential can be prevented from fluctuating and stable clamping operation becomes possible.